High-Performance Cryptographic Acceleration
Hardware-accelerated AES-128 CBC, SHA-256, and ECDSA-256 — measured on TC375 with a 100 MHz HSM core: AES-128 CBC HW 4,065 op/s (1 KB), SHA-256 HW 19,230 op/s (1 KB), ECDSA-256 signing ~216 op/s.
Embedded & Compact
The most compact hardware root of trust for USB-C and embedded systems
Micro HSM Type-C · Embedded Root of Trust
Delivers a direct hardware root of trust with minimal deployment footprint. Cryptographic operations run in isolated hardware; keys never leave the chip.
USB-C Connection
Modern USB-C interface for fast integration and evaluation.
Embedded-Ready
Low-footprint fit for boards and embedded platforms.
Compact Form
Smallest hardware root-of-trust form for space-constrained systems.
Product Showcase
Micro HSM Type-C
Hardware-accelerated AES-128 CBC, SHA-256, and ECDSA-256 — measured on TC375 with a 100 MHz HSM core: AES-128 CBC HW 4,065 op/s (1 KB), SHA-256 HW 19,230 op/s (1 KB), ECDSA-256 signing ~216 op/s.
Hardware-based True Random Number Generator (TRNG) compliant with AIS 31 for cryptographically secure key generation and tamper-resistant key storage.
PKCS#11 (Cryptoki) for signing, verification, AES/ECDSA/ECDH, and key management; PKCS#8 for secure key import/export. Integrates with OpenSSL and enterprise stacks — private keys never leave the hardware.
Encrypted Secure Updater that can update itself as well as the application and the HSM — signed, tamper-protected update paths without insecure firmware delivery.
Detailed performance measurements of our cryptographic operations on embedded platforms.
Signature Generation
Signature Verification
Signature Generation
Signature Verification
Lower Energy Use
than external HSM modules
On-chip integration removes the need for separate HSM hardware
Cost Advantage
over discrete HSMs
Integration replaces a dedicated hardware component
Parallel Processing
for cryptographic operations
Multiple crypto operations run concurrently without blocking the CPU
Measurement conditions (HSM Performance Report v0.3): TC375 host at 300 MHz, HSM core at 100 MHz, Saleae Logic at 500 MS/s. Figures are minimally optimized measured results. Total time = start + operation + response.